Field
This disclosure relates generally to semiconductor device design verification, and more specifically, to a method for verifying design rule checks.
Related Art
As semiconductor process technology advances, semiconductor device fabrication costs increase sharply. Fabrication of a semiconductor device involves generation of a physical layout for the device. Design rule checks or design rule checking (DRC) of the physical layout is a critical step in the fabrication of the semiconductor device. DRCs are typically used with a computer aided design (CAD) tool to verify compliance of a set of design rules on a physical layout for characteristics such as, for example, size and spacing. The physical layout may be used in generating masks for fabrication of the semiconductor device. The cost for set of masks used to fabricate a semiconductor device in an advanced technology may exceed $1,000,000.00. Therefore, it is important to verify design rule checks.